`include "defines.v"

module exe_reg(

    input                     clk,
    input                     rst,
    input                     exe_stall_i,

    input  wire [`RAM_BUS]    exe_pc_i,
    input  wire [31:0]        exe_inst_i,
    input  wire               exe_rd_w_ena_i,
    input  wire [`REG_BUS]    exe_rd_w_addr_i,
    input  wire [`REG_WIDTH]  exe_rd_w_data_i,  

    input  wire [5 : 0]       exe_aluop_i,
    input  wire [`RAM_BUS]    exe_mem_addr_i,
    input  wire [`REG_WIDTH]  exe_rs2_i,       
    input  reg                exe_halt_ena_i,
    input  wire               exe_skip_i, 
    input  wire               exe_reg_valid_i,  

    output reg  [`RAM_BUS]    exe_pc_o,
    output reg  [31:0]        exe_inst_o,
    output reg                exe_rd_w_ena_o,
    output reg  [`REG_BUS]    exe_rd_w_addr_o,
    output reg  [`REG_WIDTH]  exe_rd_w_data_o,  

    output reg  [5 : 0]       exe_aluop_o,
    output reg  [`RAM_BUS]    exe_mem_addr_o,
    output reg  [`REG_WIDTH]  exe_rs2_o,       
    output reg                exe_halt_ena_o,
    output reg                exe_skip_o,

    output reg                exe_reg_valid_o

);
    always@(posedge clk)begin
        if(rst == `RST )begin
            exe_pc_o        <= 0;
            exe_inst_o      <= 0;
            exe_rd_w_ena_o  <= 0;
            exe_rd_w_addr_o <= 0;
            exe_rd_w_data_o   <= 0;  
            exe_aluop_o     <= 0;
            exe_mem_addr_o  <= 0;
            exe_rs2_o       <= 0;       
            exe_halt_ena_o  <= 0;
            exe_skip_o      <= 0;
            exe_reg_valid_o <= 0;
        end
        else if(exe_stall_i)begin
            exe_pc_o        <= exe_pc_o;
            exe_inst_o      <= exe_inst_o;
            exe_rd_w_ena_o  <= exe_rd_w_ena_o;
            exe_rd_w_addr_o <= exe_rd_w_addr_o;
            exe_rd_w_data_o   <= exe_rd_w_data_o;  
            exe_aluop_o     <= exe_aluop_o;
            exe_mem_addr_o  <= exe_mem_addr_o;
            exe_rs2_o       <= exe_rs2_o;       
            exe_halt_ena_o  <= exe_halt_ena_o;
            exe_skip_o      <= exe_skip_o;
            exe_reg_valid_o <= exe_reg_valid_o;

        end
        else begin
            exe_pc_o        <= exe_pc_i;
            exe_inst_o      <= exe_inst_i;
            exe_rd_w_ena_o  <= exe_rd_w_ena_i;
            exe_rd_w_addr_o <= exe_rd_w_addr_i;
            exe_rd_w_data_o   <= exe_rd_w_data_i;  
            exe_aluop_o     <= exe_aluop_i;
            exe_mem_addr_o  <= exe_mem_addr_i;
            exe_rs2_o       <= exe_rs2_i;       
            exe_halt_ena_o  <= exe_halt_ena_i;
            exe_skip_o      <= exe_skip_i;
            exe_reg_valid_o <= exe_reg_valid_i;
        end
    end





endmodule